Conventional nonvolatile semiconductor memory devices have elements integrated in a two-dimensional plane on a silicon substrate. Although the dimensions of one element are downscaled to increase the storage capacity of the memory, such downscaling in recent years has become difficult in regard to both cost and technology.
Conversely, collectively patterned three-dimensionally stacked memories have been proposed. In such a collectively patterned three-dimensionally stacked memory, a stacked body including alternately stacked insulating films and electrode films is provided; a silicon pillar is provided to pierce the stacked body in the stacking direction; and a charge storage layer (a memory layer) is provided between the silicon pillar and the electrode films. Thereby, memory cells are provided at the intersections between the silicon pillar and the electrode films. Further, configurations also have been proposed in which two of the silicon pillars are connected on the substrate side to form a memory string having a U-shaped configuration.
In such a collectively patterned three-dimensionally stacked memory, there is room to further improve the operational performance.